1. Field of the Invention
The present invention relates to a time AD converter and a solid-state image pickup device.
2. Description of the Related Art
As examples of time AD converters, those disclosed in Japanese Unexamined Patent Application, First Publication, No. H5-259907 and Japanese Unexamined Patent Application, First Publication, No. 2004-274157 have been known. FIG. 21 is a diagram illustrating a configuration of a time AD converter. A time AD converter 3 includes an annular delay circuit 10, a counter 12, an encoder 14, a latch circuit 16, a latch circuit 18, a latch circuit 20, and an arithmetic unit 22. In the annular delay circuit 10, one NAND circuit NAND that is an inversion circuit for activation operating as a delay unit based on a pulse signal StartP received at one input terminal thereof, and a plurality of inverter circuits INV are connected in a ring shape. The counter 12 and the encoder 14 measure an output signal from the annular delay circuit 10. The latch circuit 16 holds an output signal from the counter 12. The latch circuit 18 holds an output signal from the encoder 14. The latch circuit 20 adds an output signal from the latch circuit 16 to an output signal from the latch circuit 18, and holds an added signal. The arithmetic unit 22 calculates a difference between a previous signal and a present signal using the latch circuit 20, and outputs the difference to an external post-stage circuit.
Power is supplied to the NAND circuit NAND and the inverters INV of the annular delay circuit 10 via a power line 11a. Furthermore, an input terminal 2a of an analog signal Vin to be subject to AD-conversion is connected to the power line 11a. 
Next, the operation of the AD converter 3 will be described. The annular delay circuit 10 allows the pulse signal StartP to circulate in a ring-shaped circuit in which one NAND circuit NAND and the plurality of inverters INV are connected to each other.
The counter 12 counts the number of circulations of the pulse signal StartP in the annular delay circuit 10, and outputs a count result as binary digital data. Here, the characteristics of the annular delay circuit 10 are changed according to periods of the analog signal Vin and a clock (CLK) signal CKs. Thus, a propagation delay time of the pulse signal StartP is changed according to the periods of the analog signal Vin and the clock (CLK) signal CKs.
The encoder 14 detects a position of the pulse signal StartP circulating in the annular delay circuit 10, and outputs a detection result as binary digital data.
The latch circuit 16 latches digital data which is output from the counter 12. The latch circuit 18 latches digital data which is output from the encoder 14. The latch circuit 20 takes digital data from the latch circuit 16 as an upper bit and digital data from the latch circuit 18 as a lower bit, and adds these digital data, thereby generating binary digital data corresponding to the analog signal Vin in the period of the clock (CLK) signal CKs.
The arithmetic unit 22 calculates a difference between digital data after being held in the latch circuit 20 and digital data before being held in the latch circuit 20, and outputs the difference to the external post-stage circuit.
FIG. 22A and FIG. 22B are diagrams illustrating an analog signal Vin, a propagation delay time, and a sampling period. FIG. 22A is a diagram illustrating a change in the propagation delay time according to the analog signal Vin in the annular delay circuit 10. A vertical axis indicates the analog signal Vin and the propagation delay time. A horizontal axis indicates time. FIG. 22B illustrates that the above-mentioned AD converter 3 periodically outputs digital data DT1, DT2, DT3, . . . , based on the clock (CLK) signal CKs.
Japanese Unexamined Patent Application, First Publication, No. 2004-274157 discloses that the relationship between an analog signal Vin (a signal voltage) and a count value is corrected (hereinafter referred to as “environment correction”) using the above-mentioned AD converter according to an external environment (temperature in Japanese Unexamined Patent Application, First Publication, No. 2004-274157).
However, the time AD converter performs the above-mentioned environment correction outside the time AD converter. Therefore, the circuit size of a solid-state image pickup device using the time AD converter may be increased.